View HW-USB-FLYLEADS-G_2124526.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds593 (v1.2.1) march 17, 2011 www.xilinx.com pn 0011051 04 1 ? copyright 2008?2011 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. features ? high-performance fpga and prom programming and configuration ? includes innovative fpga-based acceleration firmware encapsulated in a small form factor pod attached to the cable ? leverages high-speed slave serial mode programming interface ? recommended for prototyping use only ? easy to use ? fully integrated and opti mized for use with xilinx? impact software ? intuitive multiple cable management from a single application ? supported on the following operating systems: - microsoft windows xp professional - microsoft windows vista - red hat enterprise linux - suse linux enterprise ? automatically senses and adapts to target i/o voltage ? interfaces to devices operating at 5v (ttl), 3.3v (lvcmos), 2.5v, 1.8v and 1.5v ? intuitive flyleads-to-cable interface labeling ? reliable ? backwards compatibility with platform cable usb, including pb-free (rohs-compliant) ? usb integrators forum (usb-if) certified ? ce and fcc compliant ? leverages industry standards, including jtag boundary-scan ieee 1149. 1, spi and usb 2.0 ? programs and configur es all xilinx devices ? xc18v00 isp proms ? platform flash xcf00s/xcf00p/xl proms ? all virtex?, spartan? and xc4000 fpga families ? xc9500 / xc9500xl / xc9500xv and coolrunner? xpla3 / coolrunner-ii cplds note: xilinx impact software is required for programming and configuration ? third-party prom device programming support ? directly programs selected serial peripheral interface (spi) flash memory devices ? indirectly programs selected spi or parallel flash memory devices via fpga jtag port ? highly optimized for use with xilinx design tools ? ise? foundation? software ? embedded development kit ? chipscope? pro analyzer ? system generator for dsp platform cable usb ii description much more than just a simple usb cable, platform cable usb ii ( figure 1 ) provides integrated firmware (hardware and software) to deliver high-performance, reliable and easy-to-perform configur ation of xilinx devices. platform cable usb ii attaches to user hardware for the purpose of configuring xilinx fpgas, programming xilinx proms and cplds, and directly programming third-party spi flash devices. in addition, the cable provides a means of indirectly programming platform flash xl, third-party spi flash memory devices, and third-party parallel nor flash memory devices via the fpga jtag port. furthermore, platform cable usb ii is a cost effective tool for debugging embedded software and firmware when used with applications such as xilin x's embedded development kit and chipscope pro analyzer. platform cable usb ii is an upgrade to and replaces platform cable usb. similar to its popular predecessor, platform cable usb ii is intended for prototyping environments only. platform cable usb ii is backwards 35 platform cable usb ii ds593 (v1.2.1) march 17, 2011
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 2 compatible with platform cable usb and is supported by all xilinx design tools that support platform cable usb. platform cable usb ii attaches to the usb port on a desktop or laptop pc using an off-the-shelf hi-speed usb a?b cable. the cable derives all operating power from the hub port controller ? no external power supply is required. note: sustained data transfer rates in a hi-speed usb environment vary according to the number of usb devices sharing the hub bandwidth. native signaling rate (480 mhz) is not directly correlated to application throughput. device configuration and programming oper ations using platform cable usb ii ar e supported by xilinx impact download software using boundary-scan (i eee 1149.1 / ieee 1532), slave serial mode , or serial periphe ral interface (spi). note: impact is bundled with foundation ise so ftware and webpack? ise software. in addition, platform cable usb ii is optimized for use with xilinx embedded development ki t, chipscope pro analyzer and system generator for dsp. when used with these software tools, the cable provides a connection to embedded target systems for hardware configuration, software download, and real-time debug and verification. target clock speeds are selectable from 750 khz to 24 mhz. platform cable usb ii attaches to target systems using a 14-conductor ribbon cable designed for high-bandwidth data transfers. an optional adapter for attach ing a flying lead set is included for ba ckward compatibility with target systems not using a ribbon cable connector. x-ref target - figure 1 figure 1: xilinx platform cable usb ii ds593_01_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 3 physical description the platform cable usb ii electronics are housed in a recyclable, fire-retardant plastic case ( figure 2 ). an internal emi shield attenuates internally gene rated emissions and protects against susceptibility to radiated emissions. operation this section describes how to connect and use platform cable usb ii. minimum host system requirements the host computer must contain a usb host controller with one or more usb ports. the controller can reside on the pc motherboard, or can be added using an expansion or pcmcia card. platform cable usb ii is designed to take full advantage of the bandwidth of usb 2.0 ports, but it is also backward- compatible with usb 1.1 ports. refer to usb hub types and cable performance, page 28 for additional information on connection environments and bandwidth. ta bl e 1 lists platform cable usb ii comp atibility with the xilinx design tools. x-ref target - figure 2 figure 2: plastic case physical description top view side view status 25.4 mm 16.5 mm 115.6 mm 53.3 mm made in u.s.a. serial xu - 12345 model dlc10 platform cable usb ii power 5v 0.15a 2mm connector signals rohs compliant vref prog cclk done din init ---- or or serial 1.5 < vref < 5.0 vdc vref vref ss tms sck tck miso tdo mosi tdi ---- ---- spi jtag wp halt gnd gnd gnd gnd gnd ---- pgnd ds593_02_021908 hi-speed certified usb ?
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 4 the minimum system requ irements for these applications are located on the xilinx website at: http://www.xilinx.com/products/desig n_resources/desig n_tool/index.htm note: to receive the current enhancements and bug fixes, xilinx recomme nds using the newest version of a tool and applying the latest service pack. operating power platform cable usb ii is a bus-powered device (drawing less than 150 ma from the host usb port under all operating conditions), automati cally adapting to the capabilities of the host usb port to achieve the highest possible performance. platform cable usb ii enumerates on any usb port type: usb ports on root hubs, external bus-powered hubs, external self- powered hubs and legacy usb 1.1 hubs (see usb hub types and cable performance, page 28 ). however, performance is not optimal when attached to usb 1.1 hubs (refer to hot plug and play, page 5 for an explanation of usb enumeration). device driver installation for a complete guide to installation of the platform cable usb ii refer to ug344 , usb cable installation guide . a proprietary device driver is required to use platform cable usb ii. this driver is automati cally installed when a supported xilinx design tool is installed. note: automatic driver installation is available beginning with version 10.1 of xilinx design tools. for earlier versions, a driver i nstaller must be run prior to using the cable. refer to the usb cable installation guide for instructions on downloading and running the installer. firmware updates the platform cable usb ii firmware resides in an usb micr ocontroller and a fpga/prom. the microcontroller is ram- based and firmware is downloaded each time the cable is co nnected and detected by the host operating system. additional firmware can also be downloaded to the microcontroller once a design tool establishes a connection with the cable. the usb protocol guarantees that the firmware is successfully downloaded. upgraded firmware for the usb microcontroller is periodically distributed in xilinx desi gn tool releases or, on rare occasions, in a xilinx answer record . in most cases, an upgrade requires replacing one or more of the design tool's application files and depending on operating system, one or more cable driver files. platform cable usb ii contains a xilinx spartan-3a fpga with an in-system programmable xilinx xcf02s prom. each time a design tool establishes a connection with the cable, the firmware version stored in the prom is examined. the prom is automatically reprogrammed over the cable if the firmware ve rsion is out of date. if an update is required, the design tool displays the following warning message: warning: usb cable firmware must be updated. this operation may take up to 40 seconds. do not stop the process or disconnect the cable prior to completion. the cable status led will be red for the duration of the update process. similarly, upgraded firmware for the fpga /prom is periodically distributed in x ilinx design tool releases or, on rare occasions, in a xilinx answer record . in most cases, an upgrade requires replacing a single design tool application file. the prom is reprogrammed with the new firmware the next time the tool connects to the cable. prom reprogramming takes ta bl e 1 : platform cable usb ii software compatibility software version ise foundation / ise webpack 6.3i sp3 and later chipscope pro analyzer 6.3i sp3 and later embedded development kit 7.1i and later system generator for dsp 8.1i and later notes: 1. an installer must be run to enable platform cable usb ii for use with xilinx design tools prior to 10.1. refer to device driver installation, page 4 for additional details.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 5 approximately 40 seconds over a usb 2.0 port and 60 seconds over a usb 1.1 port. reprogramming times vary depending on the xilinx design tool version, the type of usb port and the performance of the host system. during a prom update, the cabl e's status led illuminates red ( figure 8, page 10 ), and a progress bar indicates communication activity. prom updates should never be interrupted. when an update is complete, the status led returns to either amber or green, and the cable is ready for normal operation. hot plug and play platform cable usb ii can be attached and removed from the host computer without the need to power-down or reboot. there is a momentary delay after connecti ng the cable to an available port before the status led illuminates ? this process is called enumeration. connecting to the cable in impact this section describes some of the ways to connect to platform cable usb ii using the xilinx impact graphical user interface (gui). for cable communication us ing other xilinx design tools or methods, please refer to the appropriate software user guide. select a flow from the impact gui, select a flow on the ?modes? tab ( figure 3 ). double-click on the desired flow. note: for a description of the different flows, please refer to impact help . establishing a connection once a flow is selected, there are a number of ways to establish a connection with the cable. two common options are described here: option 1: cable auto connect to auto connect the cable, select output cable auto connect ( figure 4 ). note: during the auto-connect sequence, impact selects parallel cable iv (pc4) as the active cable if both pc4 and platform cable usb ii are connected to the same host system . if two or more usb cables are connected to the same host, the active cable is the first usb cable physically connected to the host system. see multiple usb cable management, page 7 , for information on controlling more than one usb cable from a single application. x-ref target - figure 3 figure 3: impact (9.2i) modes tab ds593_03_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 6 option 2: manual cable connect to manually connect the cable, select output cable setup . select the xilinx usb cable radio button in the cable communication setup dialog box ( figure 5 ). it is necessary to perform a cable disconnect when switching from boundary scan or direct spi configuration mode to slave-serial mode, or vice versa. impact can be disconnected from the cable using output cable disconnect ( figure 4, page 6 ). after the mode switch is complete, reestablish the cable connection using the output cable setup dialog. it is not necessary, however, to perform a cable disconnect when switching between boundary-scan and direct spi configuration modes. x-ref target - figure 4 figure 4: impact (9.2i) output pull-down menu x-ref target - figure 5 figure 5: impact (10.1) cable communication setup ds593_04_021408 ds593_05_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 7 if an impact session is active when an output cable disconnect or output disconnect all cables operation is performed, or if the cable is physically disconnected from the host system, the cable status bar ( figure 7, page 9 ) at the bottom, right-hand edge of the gui immediately indicates "no cable connection." xilinx design tools employ system semaph ores to manage access to xilinx cabl es, allowing multiple applications to simultaneously access (connect to) a single cable (but only one application can perform cable operations at a given time). for example, assume two instances of impact (instance a and instance b) are connected to a single cable. if a begins a programming operation, and b then attempts a programming operation, b is temporarily blocked from accessing the cable. b receives a message indicating that the cable is locked, and the operation must be attempted again later. multiple usb cable management platform cable usb ii contains a 64-bit electronic serial nu mber used by applications to uniquely identify and access a specific usb cable when multiple usb cables (up to 127) are connected to the same host. impact provides a dialog box ( figure 6, page 7 ) allowing users to select a specific cable from a list of attached cables. when one of the cables in the list is highlighted, the status led on the appropriate cable blinks, allowing users to make a logical-to-physical association. when the desired cable is connected and the dialog box closed, the status led no longer blinks. the cable setup information dialog box ( figure 6 ) appears when the advanced usb cable setup button is pressed in the cable communication setup dialog box ( figure 5 ). note: the multiple usb cable management feature is only available in im pact version 10.1 and later. refer to the impact section of xilinx ise software manuals for additional details on this feature. configuration clock speed the platform cable usb ii configuration clock (tck_cclk_sck) frequency is selectable. ta b l e 2 shows the complete set of available tck_cclk_sck speed selections. x-ref target - figure 6 figure 6: impact (10.1) cable setup information ta bl e 2 : configuration speed selections tck_cclk_sck frequency units 24 mhz 12 mhz 6 (default) mhz 3mhz 1.5 mhz 750 khz ds593_06_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 8 impact 7.1i (and later) provides a feature wherein the bsdl file of each device in a target jtag chain is scanned to determine the maximum boundary-scan clock (jtag tck) frequency. impact 7.1i (and later) automatically restricts the available tck_cclk_sck selections to frequencies less than or equal to the slowest device in the chain. by default, impact 7.1i (or later) selects either 6 mhz or the highest common frequency when any device in the jtag chain is not capable of 6 mhz operation. ta bl e 3 shows the maximum supported jtag tck freq uency for a variety of xilinx devices. see the device data sheet or bsdl file for maximum jtag tck specifications. note: certain xilinx design tools and impact versions earlier than 7. 1i do not restrict the tck_cclk_sck selections in jtag mode. accordingly, users should take care to select a tck_cclk_sck frequency matching the jtag tck specifications for the slowest dev ice in the target chain. in slave serial or direct spi configuration mode, the tc k_cclk_sck speed can be set to any one of the available selections. by default, the tck_cclk_sck speed is set to 6 mhz. users should take care to select a tck_cclk_sck frequency matching the slave serial clock (cclk or spi clock) specification of the target device. ta bl e 3 : maximum jtag clock frequencies device family maximum jtag clock frequency (mhz) xc9500/xl/xv 10 xpla3 10 coolrunner-ii 33 xc18v00 10 xcf00s/xcf00p 15 virtex 33 virtex-ii 33 virtex-ii pro 33 virtex-4 33 virtex-5 33 spartan 5 spartan-ii 33 spartan-3 33 spartan-3a 33 spartan-3an (50, 200 and 400 densities) 33 spartan-3an (700 and 1400 densities) 20 spartan-3e 30
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 9 impact cable status bar a status bar on the bottom edge of the impact gui ( figure 7 ) provides information about cable operating conditions. for example, if the host port is usb 2.0, platform cable usb ii connects at hi-speed and the status bar shows usb-hs. if the host port is usb 1.1, platform cable usb ii connects at full- speed, and the status bar shows usb-fs. finally, the status bar displays the active cable and tck_cclk_sck frequency. status indicator platform cable usb ii uses a tri-color status led to indicate the presence of target voltage and to indicate that a cable firmware update is in progress ( figure 8 ). when the cable is connected (using a ribbon cable, or flying le ads) to a mating connector on the target system, the status led is illuminated as a function of the voltage present on pin 2 (v ref ). users must design their system hardware with pin 2 attached to a voltage plane suppling the jtag, spi, or slave serial pins on the target device(s). some devices have separate power pins for this purpose (v aux ), while others have a common supply for both v ccio and the jtag pins (tck, tms, tdi, and tdo). refer to the target device data sheet for details on jtag, slave serial or spi pins. the status led is amber when any one or more of the following conditions exist: ? the cable is not connected to a target system ? the target system is not powered ? the voltage on the v ref pin is +1.3v. the status led is green when all of the following conditions exist: ? the cable is connected to a target system ? the target system is powered ? the voltage on the v ref pin is +1.5v. note: there is 200 mv of hysteresis in the v ref detection circuit. if v ref drops below 1.3v, the status led turns amber and does not turn green until v ref is raised above 1.5v. the status led is red whenever a cable firmware update is in progress. x-ref target - figure 7 figure 7: impact (10.1) cable status bar ds593_07_021908
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 10 the status led is off whenever platform cable usb ii enters a suspend state (see system suspend, page 11 ), is disconnected from a usb port, or is connected to an un-powered usb port. ta bl e 4 summarizes the various status led states. ta bl e 4 : interpreting the status led led color led state condition off continuous host power off amber continuous target v ref 1.3v amber blinking ta r g e t v ref 1.3v and multiple cable identification active green continuous target vref 1.5v green blinking target vref 1.5v and multiple cable identification active red continuous fpga firmware update in progress x-ref target - figure 8 figure 8: cable status led amber indicates no target voltage (v ref ) green indicates target voltage (v ref ) present red indicates cable firmware update ds593_08_120307
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 11 system suspend the cable's status led is extinguished when the host system en ters a suspend (power-saving) state. a system can suspend for a number of reasons. for example: ? the user puts the host system into standby or hibernate. ? the suspend function key on a laptop computer is pressed. ? the display panel of a laptop is closed. ? the host system is configured to suspend (standby or hibernate) after a specified amount of inactivity. the current drawn by the cable while suspended depends on the type of suspend state: standby or hibernate. while the host system is in standby, the cable draws approximately 350 a from the usb port. when the host is hibernating, all power is removed from the usb ports so the cable draws no current while in this state. the target interface output drivers are not powered while the host is suspended. these signals float to any dc bias level provided by the target hardware during suspend. if an impact (10.1 or later) operation is in progress when suspend is attempted, impact displays a message ( figure 9 ) indicating that suspend is blocked until the operation is complete or manually aborted. note: this feature is not supported in earlier versions of impact, whil e impact is operating in batch mode, or by other xilinx design tools. in these cases, it is recommended that suspend be disabled in the host system when performing long, continuous operation s. the cable is automatically disconnected when the host system is suspended. a reconnect is necessary when the host re- awakens from the suspend state (see connecting to the cable in impact, page 5 ). platform cable usb ii connections this section discusses physical connections from platfo rm cable usb ii to the host pc and the target system. high performance ribbon cable a 6-inch ribbon cable is supplied and recommended for connection to target systems ( figure 10 ). the cable incorporates multiple signal-ground pairs and facilitates error-free connecti ons. the xilinx product number for the 6-inch ribbon cable is hw-ribbon14. to take advantage of the ribbon cable, a mating connector must be incorporated into the target system. this connector is normally installed only during prototype checkout. when the pr oduction hardware is functional and the isp devices can be configured from alternate sources, the connector can be eliminated to reduce cost. maintaining the footprint for this connector is recommended if space permits. x-ref target - figure 9 figure 9: suspend warning when impact (10.1 or later) is busy ds593_09_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 12 the connector is a 2-mm shrouded keyed header. see table 5, page 14 for vendor part numbers and pin assignments. flying wire adapter an adapter with wires ( figure 11 ) is provided for attachment to legacy target systems that do not incorporate a shrouded 2- mm connector. the adapter makes it possible to use flying wires for connections to distributed terminals on a target system. the adapter is a small circuit board with two connectors ( figure 12 ). the connector on the bottom side of the adapter mates with the 14-pin platform cable usb ii male 2-mm connector. a 7-pin right-angle header on the top side of the adapter mates with the standard x ilinx flying wire set. note: this method of connection is not recommended because it can result in poor signal integrity. additionally, damage can result if the leads are unintentionally connected to high voltages. the xilinx product number for the fl ying wire set is HW-USB-FLYLEADS-G. x-ref target - figure 10 notes: 1. ribbon cable: 14-pin conductor, 1.0 mm center, round-conductor fl at cable, 28 awg (7 x 36) stranded conductors, gray pvc with pi n 1 edge marked. 2. 2-mm ribbon female polarized connector, idc connection to ribbon. contacts are beryllium copper plated 30 micro-inches gold p lating over 50-micro-inches nickel. the connectors mate to 0.5-mm square posts on 2-mm centers. figure 10: high performance ribbon cable x-ref target - figure 11 figure 11: flying wire adaptor (top) with wires ds593_10_112607 status made in u.s.a. serial xu - 12345 model dlc10 platform cable usb ii power 5v 0.15a 2mm connector signals rohs compliant vref prog cclk done din init ---- or or serial 1.5 < vref < 5.0 vdc vref vref ss tms sck tck miso tdo mosi tdi ---- ---- spi jtag wp halt gnd gnd gnd gnd gnd ---- pgnd hi-speed certified usb ? jtag / serial / spi vref / vref / vref gnd / gnd / gnd tck / cclk / sck tdo / done / m iso tdi / din / m os i tm s / prog / ss halt / init / wp adapter ds593_11_021908
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 13 physical connection to the host each platform cable usb ii includes a detachable, hi-speed-usb-certified, 1.8-meter a?b cable ( figure 13 ). under no circumstances should user-supplied cables exceed 5 meters. sub-channel cables (intended for low-speed 1.5 mb/s signaling) should not be used with platform cable usb ii. a standard series b receptacle ( figure 13 ) is incorporated into the case for mating with the detachable hi-speed a?b cable. a separate chassis ground is attached to the a?b cable drain wire and returns esd current to the host system ground. x-ref target - figure 12 figure 12: flying wire adapter (side) without wires x-ref target - figure 13 figure 13: standard a-b host interface cable and series b receptacle ds593_12_012508 adapter circuit board ds593_13_112607
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 14 target interface connectors mating connectors for attachment of the high-performance ribbon cable to a ta rget system are available in both through-hole and surface mount configurations ( figure 14 ). shrouded and keyed versions should always be used to guarantee proper orientation when inserting the cable. the connector requires only 105 mm 2 of board space. the target system voltage applied to pin 2 of this connector is used as a power source for the output buffers that drive the output pins (see target interface reference voltage and signals, page 19 ). table 5, page 14 provides some third-party sources for mating connectors that are compatible with the platform cable usb ii ribbon cable. x-ref target - figure 14 figure 14: target interface connector dimensions and signal assignments ta bl e 5 : mating connectors for 2 mm pitch, 14-conductor ribbon cable manufacturer (1) smt, vertical through-hole, vertical through-hole, right angle web site molex 87832-1420 87831-1420 87833-1420 www.molex.com fci 98424-g52-14 98414- g06-14 98464-g61-14 www.fciconnect.com comm con connectors 2475-14g2 2422-14g2 2401r-g2-14 www.commcon.com notes: 1. some manufacturer pin assignments do not conform to xilinx pin assignments. please refer to the manufacturer?s data sheet for more information. 2. additional ribbon cables can be purchased separately from the xilinx online store . pgnd gnd gnd gnd gnd gnd nc tdi tdo tck tms vref halt 7.59 mm 6.30 mm 12.00 mm 2.00 mm 13 11 9 7 5 3 1 12 10 8 6 4 2 14 nc nc mosi din miso done sck cclk ss prog vref vref wp init jtag spi slave serial typ. 16.66 mm 2.00 mm 0.50 mm ds593_14_012508
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 15 target system connections this section provides examples of the various configuration topologies supported by platform cable usb ii. each example incorporates the 2-mm connector (see target interface connectors, page 14 ) as the cable interface. diagrams in this section provide a functional relationship between the cable interface and the target devices. note: signal integrity is not considered in these examples. refer to signal integrity, page 27 for details on buffering and termination. jtag and slave serial multiple devices can be cascaded wh en using either a jtag or slave- serial topology in target systems. figure 15 and figure 17, page 17 show typical routing for jtag and slave serial topologies, respectively. platform cable usb ii provides a multi-use signal on it s target interface connector called pseudo ground (pgnd). the pgnd pin is connected to an open-drain driver (see pseudo ground signal, page 22 ); hence, it is either low or high-z. the behavior of pgnd is determined by the host application connected to the cable. in impact, pgnd is active-low during jtag, slave serial and spi operations (for example, programming, configuration, read back, etc.) and high-z when the cable is idle. figure 16, page 16 shows a typical use of pgnd as a control signal to manage a target system?s jtag chain. pgnd drives the select (s) term on a set of multiplexers that switch between the primary configuration source and the cable. when pgnd is active-low, the cable drives the jtag chain. when pgnd is high-z, the primary configuration source drives the jtag chain. this capability allows platform cabl e usb ii to remain attached to the target system while remaining isolated from the primary configuration source. a similar scheme can be used with slave serial topologies. pgnd control is available only in impact versions 10.1 and later. pgnd remains high -z in earlier versions of impact and in xilinx design tools where the pgnd signal is not supported. the done pin on fpgas can be programmed to be an open-drain or active driver. for cascaded slave serial topologies, an external pull-up resistor should be used, and all devices should be programmed for open-drain operation. x-ref target - figure 15 notes: 1. example implies that v cco , v ccj , and v ccaux for various devices are set to the same voltage. refer to the device data sheet for the appropriate jtag voltage-supply levels. 2. attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11. figure 15: example of jtag chain topology isp prom tdo tdi tck tms fpga ds593_15_011508 tdi tck tms cpld tdo tdi tck tms tms tck tdi tdo gnd (2 ) v ref 2 * 8 10 4 6 2-mm connector tdo v ccaux (1)
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 16 x-ref target - figure 16 notes: 1. example implies that v cco , v ccj , and/or v ccaux for various devices in the jtag chain are set to the same voltage. 2. attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11. 3. the cable uses an open-drain driver to control the pseudo grou nd (pgnd) signal ? an external pull-up resistor is required. 4. assumes that the multiplexor supply voltages pins are connected to v ccaux . 5. pin 13 is grounded on legacy xilinx usb cables (models dlc9, dlc9g and dlc9lp), and parallel cable iv (model dlc7). these cab les need to be manually detached from the 2-mm connector to allow the primary configuration source to have access to the jtag chain . figure 16: example using pgnd in a jtag chain 8 2 10 4 6 13 * v ref tdo tdi tms tck pgnd (5) gnd (2) jtag chain tdi tdo tms tck tms tdi tdo tck a b s y mux truth table s output hy = a ly = b a b s y a b y s configuration source (primary) 2-mm connector platform cable usb ii (secondary) v ccaux (1) 1 k required pull-up (3) ds593_16_021408 (4) (4) (4) 10 k v ccaux 10 k 10 k v ccaux
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 17 direct spi platform cable usb ii can connect dire ctly to a single spi flash device. figure 18, page 18 shows an example spi flash connection. xapp951 , configuring xilinx fpgas with spi serial flash provides additional details of the cable connections necessary to program a fpga bitstream into a spi flash device. note: see configuring xilinx fpgas with spi serial flash for a list of su pported spi devices. by connecting pgnd to prog_b of the fpga ( figure 17 ), the fpga can be commanded to set its spi signals to high-z while the cable programs a spi flash device. pgnd is pulled lo w when the cable is driving its spi signals in spi mode and set to high-z when the cable is not driving its spi signals. pgnd eliminates the need for a hardware jumper to ground on the prog_b signal and the need for additional control logic. pgnd is controlled by an open-drain driver. note: pgnd control for spi programming is available in impact versions 9.2i and later. x-ref target - figure 17 notes: 1. set mode pins (m2-m0) on each fpga to slave-serial mode when using the usb cable, so the cclk is treated as an input. 2. example uses generalized nomenclature for the voltages-supply levels. refer to the device data sheet for the appropriate seri al configuration voltage-supply levels. 3. attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11. 4. a pull-up is required when two or more device s are cascaded and programmed for open-drain operation. figure 17: example of cascaded slave-serial topology fpga 1 fpga 2 fpga n dout din cclk (1) done init dout din cclk (1) done init dout din cclk (1) done init init cclk din done prog prog prog prog v ccaux (2) v ccaux (2) v cco (2) gnd (3) v ref 2 6 4 10 14 8 * 2-mm connector ds593_17_021408 470 (4 )
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 18 indirect spi when used with xilinx design tools, platform cable usb ii can be used to indirect ly program some thir d-party spi serial flash proms via the target fpga's jtag port. for a complete description on using platform cable usb ii for indirect programming of third-party spi serial flash proms and for a complete list of supported spi serial flash memories, refer to xapp974 , indirect programming of spi serial flash proms with spartan-3a fpgas . indirect bpi when used with xilinx design tools, platform cable usb ii can be used to indirect ly program platform flash xl, or some third-party nor flash memories (bpi proms) via the target fpga's jtag port. for a description of the indirect platform flash programming solution, see ug438 , platform flash xl user guide . x-ref target - figure 18 notes: 1. the pin names for a st microsystems m25pxx serial flash device are shown in this example. spi flash devices from other vendor s can have different pin names and requirements. refer to the spi flash data sheet for the equivalent pins and device requirements. 2. the example shows the interconnect and device requirements for a xilinx spartan-3e fp ga. other spi-capable fpgas can have dif ferent pin names and requirements. please refer to the fpga data sheet for equivalent pins and device requirements. 3. the cable uses an open-drain driver to control the pseudo grou nd (pgnd) signal ? an external pull-up resistor is required. 4. attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9 and 11. 5. typically, an fpga and other slave spi devices (not shown) are connected to the spi bus. the other devices on the spi bus mus t be disabled when the cable is connected to the 2-mm connector to avoid signal contention. when a xilinx fpga is connected to the spi bus, t he cable holds the fpga prog_b pin low to insure the fpga spi pins are 3-stated. figure 18: example of direct spi topology mosi prog_b gnd spartan-3e (2) fpga vccint vcco_0 vcco_2 vccaux vcc w hold d din q cso_b s cclk c gnd st micro m25pxx (1) spi flash 2 8 10 4 6 13 * v ref miso mosi ss sck pgnd gnd (4) 2 mm connector + 3.3v spi bus (5) +2.5v +3.3v +1.2v +3.3v 4.7 k (3) + 2.5v ?1? ?1? ds593_18_021508
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 19 for a complete description on using platform cable usb ii for indirect programming of third-bpi proms and for a complete list of supported bpi proms, refer to xapp973 , indirect programming of bpi proms with virtex-5 fpgas . target interface reference voltage and signals target reference voltage sensing (vref) platform cable usb ii incorporates an over-voltage clamp on the v ref pin of the 2-mm ribbon cable connector. the clamped voltage (v ref_clamp ) supplies high-slew-rate buffers that drive each of the output signals (see output driver structure ). v ref must be a regulated voltage. note: do not insert a current-limiting resist or in the target system between the v ref supply and pin 2 on the 2-mm connector. when platform cable usb ii is idle, a nominal amount of current is drawn from the target system v ref . figure 19 shows the v ref current as a function of v ref voltage. no damage to platform cable usb ii occurs if the a?b cable is unplugged from the host while the ribbon cable or flying leads are attached to a powered target system. si milarly, no damage to target systems occu rs if platform cable usb ii is powered and attached to the target system wh ile the target system power is off. bidirectional signal pins platform cable usb ii provides five bidirectional si gnal pins: tdi_din_mosi, tdo_done_miso, tck_cclk_sck, tms_prog_ss and halt_int_wp. each pin incorporates the same i/o structure. the state of each pin (reading or writing) is determined by the current mode of the cable (jtag, spi or slave serial). output driver structure each output signal is routed through a nc7sz126 ultra high-speed cmos buffer ( figure 20, page 20 ). series-damping resistors (30.1 ) reduce reflections. weak pull-up resistors (20 k ) terminating at v ref_clamp maintain a defined logic level when the buffers are set to high-z. schottky diodes provide the output buffers with undershoot protection. the fpga sets the output buffers to high-z when v ref drops below 1.30 v. in addition, an over-voltage zener on v ref clamps v ref_clamp to approximately 3.9v. figure 21, page 21 shows the relationship between the output drive voltage and v ref . note: the output drivers are enabled only during cable operatio ns; otherwise, they are set to high-z between operations. xilinx design tools actively drive the outputs to logic 1 before setting the respective buffer to high-z, avoiding the possibil ity of a slow rise-time transition caused by a charge path through the pull-up resistor into parasitic capacitance on the target system.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 20 x-ref target - figure 19 figure 19: v ref current vs. v ref voltage x-ref target - figure 20 figure 20: target interface driver topology ds593_19_021408 fpga nc7sz126 output high-z control i/o pin 2-mm connector bat54 v ref_clamp v ref_clamp 30.1 20 k to input buffer ds593_20_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 21 input receive structure each input signal is routed through a nc7wz07 ultra high-speed cmos, open-drain receive buffer. series-termination resistors (499 ) provide current limit protection for positive and negative excursions. schottky diodes provide the input buffers with undershoot protection. the receive buffers are biased by an internal 1.8v power supply. see table 9, page 32 for v il and v ih specifications. the receive buffers can tolerate voltages higher than the bias voltage without damage, compensating for target system drivers in multi-device chains where the last device in the chain might be referenced to a voltage other than v ref (for example, the tdo output at the end of a jtag chain). x-ref target - figure 21 figure 21: output drive voltage vs. v ref x-ref target - figure 22 figure 22: target interface receiver topology output drive voltage (v) v ref voltage (vdc) ds593_21_021408 fpga nc7wz07 input i/o pin 2 mm connector bat54 499 to output buffer ds593_22_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 22 pseudo ground signal the pseudo ground (pgnd) pin on target interface connector is routed to a ultra-high-speed buffer with an open-drain output ( figure 23 ). a pull-up resistor is required on ta rget systems that utilize this signal. th e buffer can tolerate a pull-up voltage as high as 6.0v. halt_init_wp signal in impact platform cable usb ii provides a second multi-use signal on its target interface connector called halt_init_wp (this signal is referred to as halt when the cable is in jtag mode). the halt_init_wp pin is connected to a three-state cmos driver (see bidirectional signal pins, page 19 ). the behavior of halt_init_wp is determined by the host application connected to the cable. impact provides the option of enabling the halt pin during jtag operations ( figure 24 ). this option is accessed by c licking on the xilinx fpga in the impact gui and selecting edit set programming properties? to open the device programming properties dialog box. check ?assert cable init during programming? to enable the halt signal. when enabled in impact, halt is active-low while the cabl e is performing jtag operations on any xilinx fpga and high- z when the cable is idle. halt is active -high while jtag operations are being performed on other devices. the halt signal remains high-z when not enabled (impact default) or when the cable is in slave serial or spi modes. note: halt signal control is available in impact 9.2i and later. halt remains high-z in earlier versions of impact and in xilinx desi gn tools where the halt signal is not supported. x-ref target - figure 23 figure 23: pgnd signal fpga nc7wz07 pgnd_cntl pgnd 2-mm connector ds593_23_021508 y a input a output y h ll z
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 23 timing specifications for jtag, spi, and slave serial configuration modes, the tdi_din_mosi and tms_prog_ ss outputs change on falling edges of tck_cclk_sck ( figure 25 ). target devices sample tdi_din_mosi and tms_prog_ss on rising edges of tck_cclk_sck. the minimum setup time t tsu(min) for target device sampling of tdi_din_mosi or tms_prog_ss is: t tsu(min) = t clk/2 ? t cpd(max) = 20.8 ns ? 16.0 ns = 4.8 ns where: t clk/2 = tck_cclk_sck low time at 24 mhz, t cpd(max) = maximum tdi_din_mosi or tms_prog_ss propagation delay relative to tck_cclk_sck inherent in the output stage of the cable. reducing the tck_cclk_sck frequency increases the data setup time at the target. note: timing specifications apply when v ref = 3.3v. operations at 24 mhz might not be possible when using a v ref below 3.3v due to the increased propagation delay through t he output buffer stage of the cable. tdo/miso timing considerations designers of target systems must take care to observe specific timing requirements for tdo (jtag chains) or miso (dedicated spi in-system programming) when incorporating the 2-mm idc connector. in particular, if an open-drain or open- collector buffer is inserted between tdo (miso) and the cable, the value of the pull-up resistor at the output of such buffers must be relatively small (for example, less than 330 ) to avoid delays associated with parasitic capacitance. figure 26, page 25 and figure 27, page 26 show the timing relationship between tck and tdo. the signal tdo_smpl is an internal logic signal not available at the target interface, but is shown to highlight the location of the tdo sampling poin t. in figure 26 , the negative tck transition at g1 causes the last device in the target system jtag chain to drive tdo, which propagates to the cable at g2. the time from g1 to g2 is the sum of the propagation delays in the driver stage of the target device and the receiver stage of the cable (37 ns in this example). in figure 27 , the cursors show the total setup time (42 ns) before tdo is sampled by the cable. figure 28, page 27 is an analog representation of the logical condition shown in figure 26 and figure 27 captured at the target system. x-ref target - figure 24 figure 24: enabling the halt signal in impact (9.2i) ds593_24_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 24 note: the propagation delay from tck to tdo is 26 ns. because figure 26 shows a propagation delay of 37 ns, the difference of 11 ns is attributable exclusively to input delays in the cable. at 12 mhz, there is still su fficient setup time before the cable sampl es prior to the next negative tck transition. x-ref target - figure 25 figure 25: tdi_din_mosi and tms_prog_ss timing with respect to tck_cclk_sck tms_prog changes on negative edge of tck_cclk (g1) tdi_din changes on negative edge of tck_cclk (g2) ds593_25_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 25 x-ref target - figure 26 figure 26: tdo sampling example at 12 mhz (tdo propagation delay) ds593_26_021408 negative tck transition at g1 causes target device to change tdo state, which propagates to the cable at g2 in less than ? clock cycle in this 12-mhz example.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 26 x-ref target - figure 27 figure 27: tdo sampling example at 12 mhz (tdo setup time relative to sampling point) ds593_27_011508 tdo setup time prior to internal sampling clock (g2 ? g1) is 42ns in this 12-mhz example.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 27 signal integrity platform cable usb ii uses high-slew-rate buffers to drive its output pins. each buffer has a 30.1 series termination resistor. users should pay close attention to pcb la yout to avoid transmission line effects. visit the xilinx signal integrity central website, and see xapp361 , planning for high speed xc9500xv designs for detailed signal integrity assistance. if the target system has only one programmable device, the 2-mm connector should be located as close as possible to the target device. if there are multiple devices in a jtag or slav e-serial single chain on the target system, users should consider buffering tck_cclk_sck. differential driver/receiver pairs prov ide excellent signal quality wh en the rules identified in figure 29 are followed. buffering is essential if target devices are distributed over a large pcb area. each differential driver and/or receiver pair contributes approximately 5 ns of propagation delay. this delay is insignificant when using 12 mhz or slower clock speeds. x-ref target - figure 28 figure 28: tdo sampling example at 12 mhz (analog signals on target system) x-ref target - figure 29 figure 29: differential clock buffer example ds593_28_021408 propagation delay from a to b (26 ns) captured directly at the target represents 70% of the total propagation delay seen by the cable (figure 25). tck tdo tdo sampling point tdo sampling point sn65lvds105 four differential drivers sn65lvds2 (2) tck_cclk_sck tck_cclk_sck1 1 4 tck_cclk_sck4 ds593_29_021408 locate driver package adjacent to 2-mm connector route a & b traces for each differential pair in parallel with equal length and consistent spacing locate one receiver adacent to each target device four buffered clocks series termination resistor (20 ?30 )
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 28 each differential receiver can drive multiple target devices if there are no branches on the pcb trace and the total trace length is less than four inches. a series termination resistor should be placed adjacent to the single-ended output of the differential receiver. note: if the target chain has, for example, a jtag or slave serial t opology and a 24 mhz clock rate is desired, it is recommended that matching buffers be used for both tck_cclk_sck and tms_prog_ss. matching buffers maintains a consistent phase relationship between tck_cclk_sck and tms_prog_ss. a buffer is not needed for tdi_din_mosi, because it sees only one load. usb hub types and cable performance there are two important hub specifications affecting the performance of platform cable usb ii: maximum port current and total bandwidth. maximum port current platform cable usb ii is a bus-powered device, drawing less than 150 ma from the host usb port under all operating conditions. note: some older usb root hubs or external bus-powered hubs might restrict peripherals to 100 ma. platform cable usb ii cannot enumerate on hubs with the 100 ma restriction. total bandwidth the maximum theoretical bandwidth is 480 mb/s for a single usb 2.0 hi-speed device and 12 mb/s for a single usb 1.1 full- speed device. however, because hub bandwidth must be shared among all connected devices, actual bandwidth is in practice lower than these theoretical values. platform cable usb ii performance is optimal when enumerated on a usb 2.0 hi-speed port. hi-speed usb operation is guaranteed only if the cable is attached directly to a usb 2.0 root hub ( figure 30e ), or to an external, self-powered usb 2.0 hub connected directly to a usb 2.0 root hub ( figure 30d ). if platform cable usb ii is attached to a usb 1.1 root hub ( figure 30a ) or to usb 2.0 external hub connected to a usb 1.1 root hub ( figure 30b ), the cable enumerates as a full-speed device and cable performance is degraded. communication and protocol overhead limits any given usb device to approximately 30% of total bandwidth. for usb 1.1 hubs, the maximum achievable throughput is approximately 3.6 mb/s. certain self-powered, usb 2.0 hubs can continue to function as usb 1.1 hubs when disconnected from their external power source ( figure 30c ). when no external power source is present, these hubs draw their power from their upstream usb port. if platform cable usb ii is connected to such a hub while operating at usb 1.1 speeds, the cable enumerates as a full- speed device. furthermore, bus-powered hubs can only deliver a total of 500 ma to all connected devices. if individual ports on bus-powered hubs are limited to less than 150 ma, platform cable usb ii does not enumerate and is unavailable for use by host software applications.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 29 interface pin descriptions x-ref target - figure 30 figure 30: platform cable usb ii performance with various hub types ta bl e 6 : jtag/spi/slave serial port: 2-mm connector signals pin number mode direction (2) description jtag configuration spi programming (1) slave-serial configuration 2v ref v ref v ref in target reference voltage (3) . this pin should be connected to a voltage bus on the target system that serves the jtag, spi or slave serial interface. for example, when programming a coolrunner-ii device using jtag, v ref should be connected to the target v aux bus. 4tms ? ? out jtag test mode select . this pin is the jtag mode signal establishing appropriate tap state transitions fo r target isp devices sharing the same data stream. 6tck ? ? out jtag test clock . this pin is the clock signal for jtag operations and should be connected to the tck pin on all target isp devices sharing the same data stream. 8tdo ? ? in jtag test data out . this pin is the serial data stream received from the tdo pin on the last device in a jtag chain. 1.x root hub 12 mb/s bus speed 1.x root hub 2.0 root hub 480 mb/s bus speed 2.0 external bus-powered hub 12 mb/s bus speed 2.0 external self-powered hub 2.0 root hub 480 mb/s bus speed 2.0 external self-powered hub 500 ma 500 ma < 500 ma 500 ma 500 ma < 500 ma 2.0 root hub 500 ma 480 mb/s bus speed 500 ma (a) (b) (c) (d) (e) power ds593_30_021408 power usb ii platform cable usb ii platform cable usb ii platform cable usb ii platform cable usb ii platform cable enumerates at full speed because root hub only operates at full speed ? degraded performance due to slow bus speed enumerates at full speed because root hub only operates at full speed ? degraded performance due to slow bus speed enumerates at full speed because 2.0 external hub operates at full speed ? degraded performance due to slow bus speed. cable may not enumerate. enumerates at hi-speed ? best performance due to high bus speed. enumerates at hi-speed ? best performance due to high bus speed.
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 30 10 tdi ? ? out jtag test data in . this pin outputs the serial data stream transmitted to the tdi pin on the first device in a jtag chain. 13 pgnd ? ? out jtag pseudo ground. use of this pin is optional. pgnd is pulled low during jtag operations; otherwise, it is high-z. this pin is connected to an open-drain driver and requires a pull-up resistor on the target system. (4) 14 halt ? ? out jtag halt. use of this pin is optional. host applications can customize the behavior of this signal. see halt_init_wp signal in impact, page 22 . 4? ss ? out spi select . this pin is the active-low spi chip select signal and should be connected to the s (1) pin on the spi flash device. 6? sck ? out spi clock . this pin is the clock signal for spi operations and should be connected to the c (1) pin on the spi flash prom. 8? miso ? in spi master-input, slave-output . this pin is the target serial output data stream and should be connected to the q (1) pin on the spi flash device. 10 ? mosi ? out spi master-output slave-input . this pin outputs the target serial input data stream for spi operations and should be connected to the d (1) pin on the spi flash device. 13 ? pgnd ? out spi pseudo ground . pgnd is pulled low during spi operations; otherwise, it is high- z. when connected to prog_b on an fpga, the fpga will high-z its spi signals while the cable is programming the spi flash. this pin is connected to an open-drain driver and requires a pull-up resistor on the target system. (4) 14 ? wp ? ? spi write protect . this pin is reserved for future use. do not connect for spi programming. 4? ? progout slave serial configuration reset . this pin is used to force a reconfiguration of the target fpga(s) and should be connected to the prog_b pin of the target fpga for a single-device system, or to the prog_b pin of all fpgas in parallel in a daisy-chain configuration. 6 ? ? cclk out slave serial configuration clock . fpgas load one configuration bit per cclk cycle in slave serial mode. cclk should be connected to the ccl k pin on the target fpga for single-device configuration, or to the cclk pin of all fpgas in parallel in a daisy-chain configuration. ta bl e 6 : jtag/spi/slave serial port: 2-mm connector signals (cont?d) pin number mode direction (2) description jtag configuration spi programming (1) slave-serial configuration
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 31 platform cable usb ii op erating characteristics 8? ? done in slave serial configuration done . this pin indicates to platform cable usb ii that target fpgas have received the entire configuration bitstream and should be connected to the done pin on all fpgas in parallel for daisy-chained configurations. additional ccl k cycles are issued following the positive transition of done to insure that the configuration process is complete. 10 ? ? din out slave serial configuration data input . this pin outputs the serial input data stream for target fpgas and should be connected to the din pin of the target fpga in a single- device system, or to the din pin of the first fpga in a daisy-chain configuration. 13 ? ? pgnd out slave serial pseudo ground. use of this pin is optional. pgnd is pulled low during slave serial operations; otherwise, it is high- z. this pin is connected to an open-drain driver and requires a pull-up resistor on the target system. (4) 14 ? ? init in slave serial configuration initialization . this pin indicates that configuration memory is being cleared and should be connected to the init_b pin of the target fpga for a single-device system, or to the init_b pin on all fpgas in parallel in a daisy-chain configuration. 3, 5, 7, 9, 11 ???? digital ground . all ground pins should be connected to digital ground on the target system to minimize crosstalk. 1, 12 ? ? ? ? not connected. notes: 1. the listed spi pin names match those of spi flash devices from st microelectronics. pin names of compatible spi devices from other vendors can vary. consult the vendor's spi device data sheet for equivalent pin names. 2. the signal pins (halt_init_wp, tdi_din_mosi, tdo_done_m iso, tck_cclk_sck, tms_prog_ss) are bidirectional. their directions during cable operations are defined by the current co nfiguration or programming mode (jtag, spi or slave serial). 3. the target reference voltage must be regulated and not have a current-limiting resistor in series with the v ref pin. 4. for more details, see target system connections, page 15 and pseudo ground signal, page 22 . ta bl e 7 : absolute maximum ratings (1) symbol description conditions value units v bus usb port supply voltage 5.25 v v ref target reference voltage 6.00 v i ref target supply current v ref = 5.25v 100 ma t a ambient operating temperature 70 c ta bl e 6 : jtag/spi/slave serial port: 2-mm connector signals (cont?d) pin number mode direction (2) description jtag configuration spi programming (1) slave-serial configuration
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 32 i out dc output current (tck_cclk_sck, tms_prog_ss, tdi_di n_mosi, and init) 24 ma notes: 1. exposure to absolute rating conditions for extended periods of time can affect product reliability. the values listed in this table are stress ratings only. functional operation of the product at these or any other conditions beyond those listed under ta b l e 8 : recommended dc operating conditions is not implied or recommended. ta bl e 8 : recommended dc operating conditions symbol description conditions min max units v bus usb port supply voltage 4.00 5.25 v v ref target reference voltage 1.5 5.00 v t a ambient operating temperature 0 70 o c t stg storage temperature ?40 +85 o c ta bl e 9 : dc electrical characteristics symbol description conditions min max units i ref target supply current v ref = 3.3v 15 ma v ref = 2.5v 3 v ref = 1.8v 1 v ref = 1.5v 1 v oh high-level output voltage v ref = 3.3v; i oh = ?8 ma 2.25 v v ref = 2.5v; i oh = ?8 ma 2.15 v ref = 1.8v; i oh = ?8 ma 1.55 v ref = 1.5v; i oh = ?8 ma 1.30 v ol low-level output voltage v ref = 3.3v; i oh = 16 ma 0.40 v v ref = 2.5v; i oh = 8 ma 0.30 v ref = 1.5v; i oh = 4 ma 0.24 v ih high-level input voltage v ref = 1.5v to 3.3v 1.35 v v il low-level input voltage v ref = 1.5v to 3.3v 0.45 v i cc1 dynamic current (1) v bus = 5.25v: tck = 24 mhz 85 110 ma i cc2 dynamic current (2) v bus = 5.25v; tck = 6 mhz 85 100 ma i ccsu suspend current v bus = 5.25v 250 350 a notes: 1. operating at hi-speed on a usb 2.0 port. 2. operating at full-speed on a usb 1.1 port. ta bl e 1 0 : switching characteristics symbol description conditions min max units t clk clock period tck 750 khz 1333 ns 24 mhz 41.66 ns t cpd cable propagation delay time (tdi or tms relative to the negative edge of tck) v ref = 1.5v to 3.3v 16 ns ta bl e 7 : absolute maximum ratings (1) symbol description conditions value units
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 33 usb-if compliance platform cable usb ii is certified by the usb integrators foru m (usb-if). certification is achieved when a product passes a battery of tests required by the usb-if compliance program. these tests (p erformed at an independent test facility) measure a product's conformity with universal serial bus spec ification revision 2.0 and establish a reasonable level of t tsu target setup time (tdi or tms relative to the positive edge of tck) v ref = 1.5v to 3.3v 4.8 ns t csu cable setup time (tdo relative to the negative edge of tck) v ref = 1.5v to 3.3v 15.8 ns t tpd target propagation delay time (tdo relative to the negative edge of tck) v ref = 1.5v to 3.3v 24.6 ns x-ref target - figure 31 notes: 1. all times are in nanoseconds and are relative to the target system interface connector. 2. t tsu min is the minimum setup time guaranteed by platform cable usb ii relative to the positive edge of tck_cclk_sck. 3. t csu min is the minimum setup required by platform cable usb ii to properly sample tdo_done_miso. 4. propagation delays associated with buffers on the target system must be taken into account to satisfy the minimum setup times . figure 31: platform cable usb ii timing diagram ta bl e 1 0 : switching characteristics symbol description conditions min max units target devices samples tms_prog_ss and tdi_din_mosi on the rising edge of tck_cclk_sck t clk t tsu t cpd tck_cclk_sck tms_prog_ss / tdi_din_mosi tdo_done_miso platform cable usb ii asserts tms_prog_ss and tdi_din_mosi on the falling edge of tck_cclk_sck t tpd platform cable usb ii samples tdo_done_miso on the falling edge of tck_cclk_sck t csu target device asserts tdo_done_miso on the falling edge of tck_cclk_sck ds593_31_021408
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 34 acceptability. products that pass this level of ac ceptability are added to the usb-if integrator's list and receive the rights of usage for the usb logo. fcc notice this equipment has been tested and found to comply with the limits for a class a digital device, pursuant to part 15 of the fcc rules. these limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. this equipment generates , uses, and can radiate radio frequency energy and, if not installed and used in accordance with the data sheet, could cause harmful interference to radio communications. operation of this equipment in a residential area is likely to cause harmful interference, in which case, th e user is required to correct the interference at his own expense. industry canada information this class a digital apparatus complies with canadian ices-003. ordering information platform cable usb ii ships with each of the items shown in ta b l e 1 1 plus a 1.8-meter, hi-speed usb, a-b cable. marking information ta bl e 1 1 : ordering information item product number platform cable usb ii hw-usb-ii-g ribbon cable, 6-inch hw-ribbon14 flying wire set HW-USB-FLYLEADS-G ta bl e 1 2 : marking information model name serial prefix description dlc10 xu platform cable usb ii
platform cable usb ii ds593 (v1.2.1) march 17, 2011 www.xilinx.com 35 revision history the following table shows the revision history for this document: notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. date version description of revisions 03/03/08 1.0 initial xilinx release. 05/14/08 1.1 ? updated trademark references. ? added support for platform flash xl. 06/09/08 1.2 corrected the functional descriptions of pins 6 and 8 in table 6, page 29 . 03/17/11 1.2.1 converted document to latest template containing current xilinx logos and colors.

▲Up To Search▲

Price & Availability of HW-USB-FLYLEADS-G

	To Download HW-USB-FLYLEADS-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .